Input/Output Organization

INPUT/OUTPUT ORGANIZATION rise to powering I/O r employments I/O embrasure gossip/out institutionalize mechanism Memory-mapped I/O y pp / Programmed I/O counteracts Direct Memory Access deales Synchronous mint Asynchronous Bus I/O in CO and O/S Programmed I/O recesss DMA (Direct stock Access) A pot is a sh argond communication link, which habits one , invest of wires to connect multiple sub st valuategys. The deuce major(ip) advantages of the transport organization are versatility and meek cost. Accessing I/O tricks Most modern computers use single cumulation arrangement for connecting I/O widgets to CPU &038 Memory The peck enables exclusively the wrenchs connected to it to switch breeding Bus consists of 3 set of nisuss Address, info, watch mainframe computer places a particular cite (unique for an I/O Dev. ) on book of facts bank places Device which recognizes this speech communication moves to the commands issued on the Control cours e of studys Processor betokens for either Read / pull through The information will be placed on Data declivitys computer computer hardware to connect I/O whatsiss to b t wad porthole Circuit Address De legislationr Control Circuits Data interprets lieu interprets The Registers in I/O Interface buffer and subordination Flags in Status Registers like SIN, SOUT Registers, SIN Data Registers, like Data-IN, Data-OUT I/O user user interface for an input kink Memory Address Processor Data Control Address Add Decoders Control C t l circuits Data d t t D t and stead registers I/O /O Interface Input device (s) p ( ) Input Output mechanism h i Memory mapped I/O Programmed I/O Interrupts DMA (Direct retentiveness Access)A bus generally contains a set of project originations and a set of entropy lines. The control lines are employ to foretoken requests and ack at presentledgments, and to indicate what type of information is on the information lines. The contro l lines are employ to indicate what the bus contains and to implement the bus protocol. The selective information lines of the bus carry information between the source and the destination. This information whitethorn consist of information, complex commands, or send fores. Buses are traditionally classified as mainframe computer- memory board di i ll l ifi d buses or I/O buses or excess purposed buses (Graphics, etc. ).Processor memory buses are short, generally amply travel rapidly, and matched to the memory placement so as to maximize memory central central central mainframe computer bandwidth. I/O b buses, b contrast, discharge be lengthy, can nurture many by t t b l th h types of devices connected to them, and a lot have a wide range in the information bandwidth of the devices connected to them. I/O buses do non typically interface directly to the memory but use either a processor-memory or a backplane bus to connect to memory. The major disadvantage of a bus is that it creates a communication bottleneck possibly limiting the maximum I/O bottleneck, throughput.When I/O must pass through a single bus, the bus bandwidth of that bus limits the maximum I/O throughput. terra firma why b R h bus d i design is so difficult i diffi lt the maximum bus quicken is largely limited by physical factors the length of the bus and the sum of devices. These physical limits prevent us from emissionning the bus ar fleckrarily fast. In addition, the need to support a range of devices with widely varying latencies and data transfer rates in addition makes bus design challenging. it becomes difficult to run many parallel wires at high amphetamine due to quantify skew and reflection reflection.The ii basic contrivances for communication on the bus are synchronous and asynchronous. If a bus is synchronous (e. g. Processor-memory), it includes a measure in the control lines and a fixed protocol for communicating that is telling to the clock. g This t ype of protocol can be implemented considerably in a small finite state machine. Because the protocol is mold and involves little logic, the bus can run very fast and the interface logic will be small. Synchronous buses have two major disadvantages First, every device on the bus must run at the identical clock rate. Second, because of clock skew problems, synchronous buses cannot be eagle-eyed if they are fast. An A asynchronous b h bus i not clocked. It can accommodate a is t l k d d t wide variety of devices, and the bus can be lengthened without worrying about clock skew or synchronization problems. To coordinate the transmission of data between sender and receiver, an asynchronous bus uses a handshaking protocol. Three special control lines need for hand-shaking ReadReq Used to indicate a read request for memory. The address is put on the data lines at the same judgment of conviction.DataRdy Used t i di t th t th d t D t Rd U d to indicate that the data give-and- trade i s now ready on the di d th data lines asserted by Output/Memory and Input/I_O Device. Ack Used to acknowledge the ReadReq or the DataRdy head of the different party. I/O Dev. Memory Steps subsequently the device bodes a request by acme ReadReq and putting the address on the Data lines 1. When memory sees the ReadReq line, it reads the address from the data bus and raises Ack to indicate it has been seen. 2. As the Ack line is high I/O releases the ReadReq and data lines. g / q 3.Memory sees that ReadReq is low and drops the Ack line to acknowledge the ReadReq signal (Mem. Reading in progress now). 4. This measuring rod starts when the memory has the data ready. It places the data from the read request on the data lines and raises DataRdy. 5. The I/O device sees DataRdy, reads the data from the bus, and signals that it has the data by raising Ack. 6. On the Ack signal, M/M drops DataRdy, and releases the data lines. 7. Finally, the I/O device, beholding DataRdy go low, drops the Ack line, which indicates that the transmission is blameless. Memory mapped I/O I/O devices and the memory share the same address space the space, arrangement is called Memory-mapped I/O. In Memory-mapped I/O portions of address space are assign to I/O devices and reads and put outs to those addresses are interpreted as commands to the I/O device. DATAIN is the address of the input buffer associated with the keyboard. Move DATAIN, R0 reads the data from DATAIN and stores them into processor register R0 Move R0, DATAOUT sends the contents of register R0 to location DATAOUT g Option of special I/O address space or incorporate as a part of memory address space (address bus is same al trends).When the processor places the address and data on the memory bus, the memory system ignores the operation because the address indicates a portion of the memory space use for I/O. The device mastery, however, sees the operation, records the data, and transmits it to the device as a comman d. User programmes are p p g prevented from issuing I/O g / operations directly because the OS does not provide access to the address space assigned to the I/O devices and thus the addresses are protected by the address translation. Memory mapped I/O can also be used to transmit data by writing or reading to select addresses.The device uses the address to determine the type of command, and the data may be provided by a write or obtained by a read. A program request usually requires several erupt I/O operations. Furthermore, the processor may have to interrogate the spatial relation of the device between individual commands to determine whether the command completed success liberaly. DATAIN DATAOUT perspective CONTROL 7 6 5 4 DIRQ KIRQ DEN great deal SOUT SIN 3 2 1 0 I/O operation involving keyboard and vaunt devices Registers DATAIN, DATAOUT, STATUS, CONTROL Flags SIN, SOUT Provides position information for keyboard nd let on unit KIRQ, DIRQ Keyboard, Display Interrupt request bits DEN, KEN Keyboard, Display modify bits Programmed I/O CPU has direct control everywhere I/O S Sensing status i t t Read/write commands Transferring data CPU waits for I/O staff to complete operation Wastes CPU judgment of conviction In this matter, use apply I/O get welly manual in the processor. These I/O instructions can pose both the device compute and the command word (or the location of the command word in memory). The processor communicates the device address via a set of wires normally included as part of the I/O bus.The actual command can be transmitted over the data lines in the bus. bus (example Intel IA-32) IA-32). By making the I/O instructions illegal to execute when not in kernel or supervisor mode user programs can be mode, prevented from accessing the devices directly. The process of sporadically checking status bits to see if it is time for the next I/O operation, is called polling. Polling is the impartialst way for an I/O device to communicate with the processor processor. The I/O device simply puts the information in a Status register, register and the processor must come and get the information.The processor is totally in control and does all the work. A ISA program to read one line from the keyboard, store it in memory buffer and echo it back to the display buffer, The disadvantage of polling is that it can waste a lot of processor time because processors are so much faster than I/O devices devices. The processor may read the Status register many times, only when to make that the device has not yet completed a comparatively leaden I/O operation, or that the mouse has not budged since the last time it was polled.When the device completes an operation, we must s process read the status to determine whether it (I/O) was successful. bang in a polling interface lead to the invention of break aparts to notify the processor when an I/O device requires attention from the processor. Interrupt- operate I/O, Int errupt driven I/O employs I/O cave ins to indicate to the processor that an I/O device needs attention. When a device wants to notify the processor that it has completed round operation or needs attention, it causes the processor to be break.Interrupts I/O INTERRUPT Processor When I/O Device is ready, it sends the INTERRUPT signal to processor via a dedicated controller line Using wear we are ideally eliminating WAIT period In response to the interrupt, the processor executes the Interrupt Service Routine (ISR) solely the registers flags program counter values are freed registers, flags, by the processor in front running ISR The time required to save status &038 delayore stomach to act overhead ? Interrupt Latency p y nterrupt-acknowledge signal I/O device interface p y accomplishes this by execution of an instruction in the interrupt-service human action (ISR) that accesses a status or data register in the device interface implicitly informs the device that its i nterrupt request has been recognized. IRQ signal is then removed by device. ISR is a sub-routine may be presbyopic to a different user than the one world executed and then halted. The condition code flags and the contents of any registers used by both the interrupted program and the interrupt-service interrupt service routine are saved and restored restored.The concept of interrupts is used in operating systems and i many control applications, where processing of d in l li i h i f certain routines must be accurately timed relative to external events (e. g. real-time processing). Interrupt ironware p Pull up Pull-up resister INTR = INTR1 +.. +INTR n INTR An same circuit for an string out drain bus used to implement a open-drain common interrupt-request line Interrupt Hardware Supply pp y R INTR Processor Pull-up resister INTR 1 INTR 2 INTR 3 INTR = INTR1 +.. +INTR n GND INTR Enabling and Disabling Interrupts Device activates interrupt signal line and waits with this signal activ ated until processors attends The interrupt signal line is active during execution of ISR and till the device caused interrupt is serviced Necessary to ensure that the active signal does not lead to successive breakings ( train-triggered input) causing (level triggered the system to fall in unconditioned loop. What if the same d i h h device i interrupts again, within an ISR ? i i hi Three methods of Controlling Interrupts (single device) Ignoring interrupt Disabling interrupts Special Interrupt request line Ignoring Interrupts Processor hardware ignores the interrupt request line until the execution of the initiatory instruction of the ISR completed Using an interrupt disable instruction after the frontmost-year instruction of the ISR no hike interrupts A return from interrupt instruction is completed before further interruptions can occur Disabling Interrupts Processor mechanically disables interrupts before starting the execution of the ISR The processor saves the contents of PC and PS (status register) before performing interrupt disabling. The interrupt-enable is set to 0 no further interrupts allowed When return from interrupt instruction is executed the contents of the PS are restored from the stack, and the interrupt enable is set to 1 Special Interrupt line p p Special interrupt request line for which the interrupt intervention circuit responds only t th l di h dli i it d l to the leading edge of d f the signal Edge triggered g gg Processor receives only one request regardless of how long the line is activated N separate i t No t interrupt di bli t disabling i t instructions tiThe sequence of events involved in handling an interrupt request from a single device. Assuming that interrupts are enabled, the quest is a typical scenario 1. 1 The device raises an interrupt request request. 2. The processor interrupts the program currently being executed. t d 3. Interrupts are handicapped by changing the control bits in the PS (ex cept in the scale of edge-triggered interrupts) interrupts). 4. The device is informed that its request has been recognized, and in response, it deactivates the interrupti d di d ti t th i t t request signal. . The bodily process requested by the interrupt is performed by the interrupt-service routine. 6. Interrupts are enabled and execution of the interrupted program is resumed. Handling Multiple Devices Multiple devices can initiate interrupts p p They uses the common interrupt request line y p q Techniques are q Polling Vectored Interrupts p Interrupt Nesting Daisy Chaining y g Polling Scheme The IRQ (interrupt request) bit in the status register is set when a device is requesting an interrupt. The Interrupt service routine polls the I/O devices connected to the bus. The first device encountered with the IRQ bit set is serviced and the subroutine is invoked. Easy to implement, but also much time spent on checking the IRQ bits of all devices, though some devices may n ot be requesting service. Vectored Interrupts Device requesting an interrupt identifies itself directly to the processor The device sends a special code to the processor over the bus. The code contains the identification of the device device, starting address for the ISR, address of the branch to the ISR PC finds the ISR address from the code. To add flexibility for multiple devices same ISR is executed by the processor using a branch address to the appropriate routine device specified Interrupt Vector. An interrupt vector is the memory address of an interrupt liker, or an index into an array called an interrupt vector slacken or dispatch table a table of interrupt vectors (pointers to routines that handle interrupts).Interrupt vector tables contain the memory addresses of interrupt handlers. When an interrupt is generated, the processor saves its execution state via a context switch, and begins execution of the interrupt handler at the interrupt b i ti f th i t t h dl t th i t t vector. The Interrupt Descriptor Table ( p p (IDT) is specific to the ) p I386 architecture. It tells where the Interrupt Service Routines (ISR) are located. Each interrupt number is reticent for a specific purpose. For example, 16 of the vectors are reserved for the 16 IRQ lines.Q On PCs, the interrupt vector table (IVT or IDT) consists of 256 4-byte pointers the first 32 (0-31 or 00-1F) of which are reserved f for processor exceptions the rest f for hardware interrupts, software interrupts. This resides in the first 1 K of addressable memory. Interrupt Nesting Pre-Emption of low antecedency Interrupt by another high Pre Emption priority interrupt is known as Interrupt nesting. Di bli Disabling I t Interrupts d i t during th execution of th ISR the ti f the may not estimation devices which need immediate attention. Need a priority of IRQ devices and accepting IRQ from a high priority device. The priority level of the processor can be mixtured y y dynamically. Th e privileged instruction write in the PS (processor status word) that encodes the processors priority word), priority. Interrupt Nesting (contd. ) Pro ocessor INTR1 Device 1 INTA 1 Device 2 INTRp .. . Device p INTA p antecedence arbitrament circuit Organizing I/O devices in a prioritized mental synthesis. g g / p Each of the interrupt-request lines is assigned a different priority level level. The processor is interrupted only by a high priority device. Daisy Chaining The interrupt request line INTR is common to all the devices The interrupt quotation line INTA is connected to devices in a DAISY CHAIN way INTA propagates serially through the devices Device that is electrically closest to the processor gets high hi h priority i i Low priority device may have a danger of STARVATION INTR P Processor r Device D i 1 INTA Device D i 2 .. Device n D i Daisy Chaining with Priority Group Combining Daisy chaining and Interrupt nesting to form p priority crowd yg p Each group has different priority levels and within to each one group devices are connected in daisy chain wayINTR1 Proc cessor Device 1 Device 1 INTA 1 INTR p . . . . Device D i 1 INTA p Priority arbitration circuit Device D i 1 Arrangement of priority groups Direct Memory Access (DMA) For I/O transfer, Processor determines the status of I/O devices, by Polling Waiting for Interrupt signal Considerable overhead is incurred in to a higher place I/O transfer processing To transfer large stopovers of data at high Speed, between EXTERNAL devices &038 Main Memory, DMA approach is often used DMA controller allows data transfer directly between I/O device d i and d Memory, M with i h minimal i l intervention i i of f processor. Direct Memory Access (DMA) DMA controller acts as a Processor, but it is controlled by CPU To initiate transfer of a block of words, the processor sends the following data to controller The starting address of the memory block The word count h d Control to specify the mode of transfer such as read or write A control to start the DMA transfer DMA controller performs the requested I/O operation and sends a interrupt to the processor upon completion 1 Status and Control Starting address Word count In ? ? ? IRQ 30 IE 1 R/W 0 make DMA interface g g First register stores the starting address Second register stores Word count Third register contains status and control flags Bits and Flags R/W Done IRQ IE 1 withdraw Data transfer finishes Interrupt request Raise interrupt (enable) after Data Transfer 0 WRITE Processor Main memory Disk/DMA controller DMA controller Printer Keyboard Disk Disk mesh Interface Use of DMA Controller in a computer system Memory accesses by the processor and DMA Controller are interwoven DMA devices have higher priority then processor over BUS control speech rhythm Stealing- DMA Controller steals memory cycles from processor, though processor originates most(prenominal) memory access. Block or Burst mode- The of d ata without interruption Conflicts in DMA Processor and DMA, Two DMA controllers, try to use the Bus at the same time to access the main memory DMA controller may given exclusive access to the main memory to transfer a blockDMA and Interrupt Breakpoints During D i an I t Instruction Cycle ti C l Bus arbitration Bus mortify device that initiates data transfers on the bus. The next device can take control of the bus after the current master relinquishes control Bus Arbitration process by which the next device to become master is selected Centralized and Distributed Arbitration BBSY P Processor r BR BG1 DMA controller 1 BG2 DMA controller 2 A simple arrangement for bus arbitration using a daisy chain BR (bus request ) line open drain line the signal on this line is a logical OR of the bus request from all the g q DMA devices BG (bus grant) line processor activates this line indicating (acknowledging) to all the DMA devices (connected in daisy chain fashion) that the BUS ma y be used when its free free. BBSY (bus busy) line open collector line the current bus master i di b indicates d i devices that i i currently using h it is l i the bus by signaling this line BBSY Processor BR BG1 DMA controller 1 BG2DMA controller 2 Sequence of signals during data transfer of bus mastership Centralized Arbitration Separate unit (bus arbitration circuitry) connected to the bus Processor is normally the bus master, unless it grants bus mastership to DMA For the timing/control, in introductory slide DMA controller 2 requests and acquires bus mastership and later releases the bus. During its tenure as the bus master, it may perform one or more data transfer operations, depending on whether it is p , p g operating in the cycle stealing or block mode.After it releases the bus, the processor resumes bus mastership. Distributed Arbitration All devices waiting to use the bus has to carry out the arbitration process no central arbiter Each device on the bus is assi gned with a identification number 4-bit ane or more devices request the bus by asserting q y g the start-arbitration signal and place their identification number on the four open collector lines arbitrageur0 through ARB3 are the four open collector lines One among the four is selected using the code on the lines and one with the highest ID numberA distributed arbitration scheme Assume that two devices, A and B, having ID numbers 5 and 6, respectively, are requesting the use of the bus. Device A transmits the pattern 0101, and device B transmits the pattern 0110. p The code seen by both devices is 0111. Each device compares the pattern on the arbitration lines to its own ID, starting from the most significant bit. If it detects a loss at any bit position, it disables its drivers at that bit position and for all lower-order bits. It does so by placing a 0 at the input of these drivers drivers.In the case of our example, device A detects a difference on line ARB I. Hence, it disa bles its drivers on diff li I H i di bl i d i lines ARB 1 and ARBO. This causes the pattern on the arbitration lines to change to 0110, which means that B has won the contention. Universal Serial Bus (USB) The USB supports two speeds of operation called lowoperation, low speed (1. 5 megabits/s) and full-speed (12 megabits/s). The Th most bran-new revision of the bus specification (USB i i f h b ifi i 2. 0) introduced a third speed of operation, called high-speed (480 megabits/s).The USB has been designed to meet several key objectives -P Provide a simple, low-cost, and easy to use interconnection id i l l t d t i t ti system that overcomes the difficulties due to the limited number of I/O ports available on a computer admit a wide range of data transfer characteristics for I/O devices, including telephone and Internet connections / , g p Enhance user whatchamacallit through a plug-and-play mode of operation USB Bandwidths A low-speed rate of 1. 5 Mbit/s (183 kB/s) is defined b y USB 1. 0.It is intended primarily to save cost in lowbandwidth human interface devices (HID) such as keyboards, ( ) y , mice, and joysticks. The full-speed rate of 12 Mbit/s (1. 43 MB/s) is the full speed ( 1. 43 basic USB data rate defined by USB 1. 1. All USB hubs support full-bandwidth. A high-speed (USB 2. 0) rate of 480 Mbit/s (57 MB/s) was introduced in 2001. All hi-speed devices are capable of falling back to full bandwidth operation if necessary they are full-bandwidth backward compatible. Connectors are identical. SuperSpeed ( d (USB 3. 0) rate produces upto 4800 Mbit/s ) d bi / (572 MB/s or 5 Gbps)Each node of the manoeuvre has a device called a hub, which acts as an intercede control point between the host and the I/0 devices devices. At the root of the tree, a root hub connects the entire tree to the host computer. The leaves of the tree are the I/0 p / devices being served. The tree structure enables many devices to be connected while using only simple point-topoin t serial links. Each hub has a number of ports where devices may be connected, including other hubs. In normal operation, a hub g copies a pith that it receives from its upriver connection to all its downstream ports.As A a result, a message sent b the host computer is lt t by th h t t i broadcast to all I/O devices, but only the addressed device will respond to that message. A message from an I/O device is sent only upstream towards the root of the tree and is not seen by other devices. Hence, th USB enables th h t t communicate with the I/O H the bl the host to i t ith th devices, but it does not enable these devices to communicate with each other. The USB operates strictly on the basis of polling. A device may send a message only in response to a poll message from the host host.Hence, upstream messages do not encounter conflicts or interfere with each other, as no two devices can send other messages at the same time. This restriction allows hubs to be simple, low-cost devices. USB protocol requires that a message transmitted on a highspeed link is always transmitted p y at high speed, even when the ultimate receiver is a low-speed device. device Hence, a message intended for device D is sent at high speed from the root hub to hub A, then A forwarded at low speed to device D. The latter transfer will take a long time, during which highl ti d i hi h hi h speed traffic to other nodes is allowed to continue.Each device on the USB, whether it is a hub or an I/O device, is assigned a 7-bit address. This address is local to the USB tree and is not related in any way to the addresses used on the processor bus. A hub may have any number of devices or other hubs connected to it, and addresses are assigned arbitrarily. When a device is first connected to a hub, or when it is powered on, it has the address 0. The hardware of the hub to which this device is connected is capable of detecting that the device has been connected, and it records this f d hi fact as part o f i own status i f f its information. Periodically, the host polls each hub to collect status information and learn about new devices that may have been added or disconnected. When the host is informed that a new device has been connected, connected it uses a sequence of commands to send a reset signal on the corresponding hub port, read information from the device about its capabilities, send configuration information to the device, and assign the device a unique USB address. O d i d i th d i i dd at one time this thi sequence is completed the device begins normal operation and responds only to the new address. Read about USB protocols Isochronous traffic on USB and USB FRAME